`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Cal Poly // Engineer: Matthew Province // // Create Date: 09/25/2020 02:26:06 PM // Module Name: Lab2P1 // Project Name: Lab 2 // Target Devices: Basys3 // Description: Prof's Need More Coffee Company ////////////////////////////////////////////////////////////////////////////////// module Lab2P1( input A, input B, input C, input D, output X ); assign X = (A & ~B) | (~A & D) | (~A & B & ~C) | (~B & C) | (~D & A & C); endmodule